Related Application
This application is related to U.S. patent application Ser. No.: 08/960,777 entitled "BI-DIRECTIONAL SYNCHRONIZING BUFFER SYSTEM" filed concurrently herewith.
1. Field of the Invention
This invention relates to methods of transferring within a computer system. More specifically, this invention relates to methods of synchronizing data from a component in a first clock domain to a component in a second clock domain with a bi-directional synchronizing buffer.
2. Description of the Related Art
Within most computer systems are sets of buffers that temporarily store data as it is transferred from one component in the computer system to another. These buffers act as temporary storage areas for the data as it moves via various buses in the computer system. One type of buffer, a first in-first out (FIFO) buffer, has been used within computer systems to synchronize data transfers from one clock domain to another in the computer system. As is known, internal components of a computer system can be run at different clock frequencies. Thus, in some cases, data must be sent from a component under the control of one clock to a component that is controlled by a second clock.
For example, a high speed microprocessor may send data to a peripheral device that resides on the expansion bus of the computer system. The microprocessor might, for example, be under the control of a 200 MHz clock, while the peripheral device is running under the control of a 66 MHz clock. Thus, prior systems have placed a data buffer at the boundary between the two clock domains so that data from the microprocessor that is running at 200 MHz does not have to wait through numerous clock cycles to synchronize with the clock frequency of the peripheral device. In some current computer systems, one or more FIFO buffers are placed within a bridge circuit that lies between the microprocessor's clock domain and the peripheral device's clock domain. Data that is sent from the microprocessor at 200 MHz is temporarily stored in a FIFO buffer in the bridge circuit so that the microprocessor can continue to rapidly process data as the slower peripheral device reads data from the FIFO buffer at 66 MHz.
Obviously, at some point, the FIFO buffer will fill with data from the microprocessor and thereby cause the microprocessor to begin inserting wait states into its process until more space becomes available within the FIFO buffer. However, depending on the size of the FIFO buffer, the overall transfer time from the microprocessor to the peripheral device can be substantially reduced. It should also be recognized that data coming from the slower peripheral device can be passed in the reverse direction through a FIFO buffer before being read at high speed by the microprocessor. By using this type of system, the faster microprocessor can wait until the FIFO buffer has filled before starting to read the data at high speed. Thus, the data can be removed from the FIFO buffer at the microprocessor's full speed. However, several problems exist with the current buffer implementations used to increase the speed of transferring data between two clock domains of a computer system.
Some bridge systems, such as the one implemented in the Intel 82430 PCI chipset, include a pair of FIFO buffers to manage data transfers between an Intel Pentium.RTM. microprocessor and a Peripheral Component Interface (PCI) peripheral bus of a computer system. In these circuits, one FIFO buffer manages data transfers from the microprocessor to the peripheral bus while the other FIFO buffer manages data transfers in the opposite direction, from the peripheral bus to the microprocessor. While this implementation provides advantages over systems that have no buffering, it also possesses several disadvantages. One disadvantage in this type of system is that implementing two FIFO buffers in opposite orientations requires a large number of silicon gates. The increased gate count leads to a more expensive and less efficient system. Thus, a system that could manage bi-directional data buffering without implementing two separate FIFO buffers would be advantageous.
Another disadvantage of current FIFO buffer systems is that each piece of data is synchronized from one clock domain to another on either the input side or the output side of the FIFO buffer, depending on which component originates the FIFO clock. For example, each piece of data arriving from a high speed component to a FIFO buffer that is synchronized on the input will have to wait through several clock cycles before it is synchronized to the slower clock frequency and stored into the buffer. Alternatively, each piece of data that is sent out of a FIFO buffer that is synchronized on the output to a slower speed component will have to wait through several wait states until it is synchronized to a clock cycle on the slower component. Each of these schemes results in a data transmission delay through the FIFO buffer. Thus, there is a significant penalty imposed in these systems for individually synchronizing each piece of data on the input or output of the FIFO buffer. For this reason, current FIFO buffers do not process data efficiently. It would be advantageous to provide a system that did not require each piece of data to be individually synchronized.
In addition to the disadvantages in prior systems associated with synchronizing every piece of data individually, several other problems exist in prior systems relating to the metastability of logic gates when data is transferred between two clock domains of an integrated circuit.
Synchronization Issues
A synchronization problem exists when passing synchronous logic signals between two separate clock domains within an integrated circuit. The problem is due to a behavior of synchronous logic gates called metastability. When Application Specific Integrated Circuit (ASIC) vendors specify signal timing requirements through their logic gates, it is based on an input data signal (D input of the gate) meeting a specific setup and hold time relative to the clock edge that causes the gate to transition, and guarantee the output (Q output of the gate) to be stable within a specified period of time (output delay). If the input signal does not meet the setup and hold times specified (i.e. the signal transitions close to the clock edge), it may cause the gate to become metastable.
When a gate becomes metastable, its output oscillates rapidly between one and zero, eventually settling to a stable state. However, the logic level that the gate settles to is indeterminate and it may take significantly longer than the normally specified output delay. Obviously, a system cannot depend on the output of a gate that has become metastable because the output logic level does not correspond to the input logic level. For this reason, when an asynchronous logic signal is to be used in a synchronous manner, there is no simple way to guarantee that the signal will meet the gate setup and hold times; thus allowing the gate to go metastable. For this reason current industry practice, when synchronizing logic signals, includes passing the signal through two gates connected in series. This scheme allows the first gate to become metastable and settle out before reaching the second gate at the next clock edge. This allows the output of the second gate to have a clean transition which meets specified output delay times.
Synchronization of multiple data bits
However, several disadvantages exist in the current technology relating to passing a number of asynchronous logic signals (i.e. a data bus) through two gates to provide a stable system in a synchronous environment. One disadvantage is that providing two gates for every signal that crosses the clock boundary increases the number of silicon gates required in the device. This takes gates away from other devices and increases the manufacturing cost of the device.
Another reason for not wanting to place dual gates on every data line that crosses a clock boundary is that, as the device becomes metastable, the output logic level is indeterminate. Thus, the data value output from the second set of gates is indeterminate. Since the data being passed across the clock boundary must be sent without errors, it is unacceptable for the data level of those bits to be indeterminate. Having indeterminate data levels of bits on a data bus would lead to tremendous data errors in the information that is passed through the FIFO buffer.
What is needed in the technology is an efficient system for buffering data between two clock boundaries wherein the system does not require two gates for every data line. In addition, the technology could benefit from a system that provides these advantages and can buffer data in both directions without relying on separate registers to store the data traveling in each direction.